CACTI 6.0: A Tool to Understand Large Caches

Future processors will likely have large on-chip caches with a possibility of dedicating an entire die for on-chip storage in a 3D stacked model. With the ever growing disparity between transistor and wire delay, the properties of such large caches will primarily depend on the characteristics of the interconnection networks that connect various sub-modules of a cache. CACTI 6.0 is a significantly enhanced version of the tool that primarily focuses on interconnect design for large caches. In addition to strengthening the existing analytical model of the tool for dominant cache components, CACTI 6.0 includes two major extensions over earlier versions: First, ability to model Non-Uniform Cache Access (NUCA). Second, ability to model different types of wires, such as RC based wires with different power, delay, and area characteristics and differential low-swing buses. The report details the analytical model assumed for the newly added modules along with their validation analysis.